1. Field
The embodiments discussed herein are related to a cross-connect method and a cross-connect apparatus for performing cross-connect processing by multiple cross-connect sections.
2. Description of the Related Art
In a SONET (Synchronous Optical Network) or an SDH (Synchronous Digital Hierarchy), it is common to make a ring network configuration using, for example, a UPSR (Unidirectional Path Switched Ring).
FIG. 1 illustrates a configuration diagram of an example of a SONET ring network. In the figure, transmission apparatuses 1a to 1e are connected in a ring shape by optical transmission lines 2a to 2e to constitute a ring network.
A lot of interface cards are provided in the transmission apparatus 1a. Among the interface cards required, interface cards (OC-N cards) 3a and 3b are connected to the optical transmission lines 2a and 2e, respectively. Each of the interface cards 3a, 3b and the like are connected to a primary switch card 4a and a secondary switch card 4b, and add/drop interface cards 5a and 5b are connected to the switch cards 4a and 4b. 
In the UPSR form as illustrated in FIG. 1, signal channels (synchronous transfer modules STS-1×n) assigned to node-to-node communications on the ring network correspond to a line capacity of N channels, as a whole. On the switch cards 4a and 4b in charge of line setting (cross-connect) within the transmission apparatus and various protection switching processings, when line setting is performed in the direction from the branch side (add/drop) to the network side (UPSR), a redundant configuration is adopted in which, by assigning the same channel signal to the east side (the transmission line 2a side) and the west side (the transmission line 2b side), transmission is performed via different routes on the ring network. In a transmission apparatus on the channel signal terminal side, line setting is performed in the direction from the network side to the branch side, and a route with a better line quality is selected for each path on the basis of the state of detection of a path alarm and the like of the routes.
In such a SONET/SDH optical transmission apparatus, increase in the line processing capacity of the apparatus is realized by adopting a division processing configuration using multiple chips (devices) for a cross-connect processing function.
The cross-connect processing requires connection processing for each channels (for example, STS-1) set as the unit of cross-connect processing in accordance with the same line setting information. Therefore, in a division processing method using multiple chips, processing for dividing 1-byte (8-bit) information for nibble (4-bit), dibit (2-bit) or 1-bit paths is performed, and a chip configuration suitable therefor is adopted.
That is, a two-chip configuration is adopted for the nibble processing, a four-chip configuration is adopted for the dibit processing, and an eight-chip configuration is adopted for the bit processing. In order to perform cross-connect processing for the whole line capacity which can be held by the transmission apparatus, it depends on the processing capacity of the device which performs core cross-connect processing. However, in the case where the processing capacity of one chip is not sufficient for the processing, the processing is realized, for example, by performing two-division processing as illustrated in FIG. 2.
FIG. 2 illustrates a block configuration diagram of an example of a typical switch card. In the figure, each of interface cards 21-1 to 21-n is connected to the network side or the branch side. Each of the interface cards 21-1 to 21-n performs optical-electrical conversion and electrical-optical conversion. Each interface card performs optical-electrical conversion of an optical signal received from the network side or the branch side, and provides it to a backplane interface section 24 of a switch card 23 via a backplane 22.
The backplane interface section 24 performs two-division processing (format conversion and bit array conversion) of the signals and provides the signals to cross-connect sections (TSI) 25a and 25b. The cross-connect sections 25a and 25b perform cross-connect processing and provides the signals to the backplane interface section 24.
The backplane interface section 24 performs multiplexing processing (inverse format conversion and inverse bit array conversion) of signals provided from the cross-connect sections 25a and 25b. The multiplexing-processed signals are provided for the interface cards 21-1 to 21-n via the backplane 22, electrical-optical conversion processed and outputted to the network side or the branch side.
As illustrated in FIG. 3, in the cross-connect processing operation, 1-byte information is provided for the two-chip cross-connect sections 25a and 25b by paths obtained by dividing the 1-byte information into two (in nibbles) for each channel, and the same line setting control signal is provided for the cross-connect sections 25a and 25b from a controller 27. Thereby, processing for connecting to the same channel is performed at the same time. In comparison with ordinary cross-connect processing in which processing is performed for each byte (8 bits) for each channel, virtual byte processing is realized by the cross-connect sections 25a and 25b, which are configured to perform two-division processing, performing linked processing operations for each nibble.
In FIG. 3, the expression of the signal arrays indicates the row of signals when the cross-connect division processing is performed (byte-nibble conversion) and the flow of the cross-connect processing. Each of signals a7-a0 to g7-g0 expresses a channel which is the unit targeted by the cross-connect processing. Cross-connect processing for each channel is performed for the backplane 22 by, after rearranging each signal provided from the backplane 22 side from a byte array to a nibble array, dividing the signals the MSB side and the LSB side and performing cross-connect processing at the cross-connect sections 25a and 25b and returning the array to the original byte array at the backplane interface section 24.
FIG. 4 illustrates that, since a configuration of division processing by the cross-connect sections 25a and 25b is adopted, each chip has surplus processing capability.
As a related technique, Japanese Patent Laid-Open No. 08-223241 discusses a technique in which means for stopping an auxiliary function section is provided for a transmission apparatus having a function requisite for transmitting a main signal and an auxiliary function which is not requisite, to reduce the power consumption of the apparatus.
A typical technique is provided in which, when bulk cross connect is configured using multiple racks, and a redundancy system is further configured, the number of secondary systems is reduced to reduce the power consumption of the whole system by setting the ratio of primary and secondary cross-connect means is set not as 1:1 but as 1:N.
As a technique related thereto, there is a technique disclosed in Japanese Patent Laid-Open No. 10-257580.